Generalized compile-time circuit signatures

Purpose and scope

Proposes circuit signatures with multiple disjoint register views and compile-time size parameters. The aim is source reuse and checked resource ownership.

Core design rules

• const ...: Int arguments and QReg<E> widths are resolved at the call site.
• Disjoint views of one physical register may be accepted; overlapping views are rejected.
• Specialization is deterministic and retains source mapping plus adjoint, bounded ctrl and pow semantics.

Example from the original

This example illustrates the design recorded in the original. It is not by itself a claim of executable or stable support; check required options and the current version.

circuit entangle<const N: Int>(
  control: QReg<N>,
  target: QReg<N>,
  theta: Angle
) {
  for i in 0..N {
    Ry(target[i], theta);
    CNOT(control[i], target[i]);
  }
}

Limits and interpretation

• Runtime sizing, recursion, dynamic calls and measurement/training inside a generic circuit are outside this slice.
• A generic signature does not imply generic QPE/Simon/Shor readiness or larger simulation capacity.

Status and implementation boundary

The original is proposed. Generic signatures, oracle types and concrete circuit support are separate contracts; examine exact-version dependencies and current capabilities together.